Kevin Cameron
Fixing things
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About
Career
20 roles
Samsung
Senior Verification Engineer
2025-01 – 2025-06
Developed methodology for RTL and software programming of an FPGA-based CXL accelerator.
Lightelligence
Software Engineer
2023-01 – Present
Performed RISC-V processor extension modeling.
Cirrus Logic
Software Engineer
2022-01 – 2023-12
Developed behavioral models for switch-capacitor PMIC components.
Microsoft
Software Engineer
2021-01 – 2022-12
Performed C model verification.
Facebook
Software Engineer
2019-01 – 2020-12
Performed RISC-V extension modeling and embedded processor verification.
Qualcomm
Verification Engineer
2018-01 – 2018-12
Performed RF and analog verification at Qualcomm QCA.
Cadence
Verification Engineer
2018-01 – 2019-12
Performed processor verification at Cadence Palladium.
Samsung
Software Engineer
2016-01 – 2016-12
Developed GPU models at Samsung's Advanced Processor Lab and reduced build and regression cycle time from one hour to ten minutes through Perl and CMake scripting improvements.
Silvaco
Senior Consultant
2015-01 – 2015-12
Achieved a ten-times speed improvement to mixed-signal simulator analog-to-digital synchronization in the Harmony product.
Synopsys
Senior Staff R&D Engineer
2014-01 – 2014-12
Focused on mixed-signal simulation architecture for VCS-MX.
Intel
Verification Engineer
2013-01 – 2013-12
Built VHDL analog circuit models for RF components in the Mobility Group.
Fusion-io
Software Engineer
2011-01 – 2012-12
TrueCircuits
Software Engineer
2008-01 – 2009-12
Achieved a five-times speed increase in GDSII conversion through distributed parallel processing techniques.
Sonics Inc.
Software Engineer
2005-01 – 2007-12
Created parallel build scripts for use with LSF, developed C++ protocol checkers for AMBA, AXI, and OCP standards, and ported tools to 64-bit architectures.
Altera Corporation
Software Engineer
2004-01 – 2005-12
Improved simulation models for FPGA hard macros such as Multiply-Accumulate units and contributed to simulator development strategy.
CPU Technology
EDA Software Engineer
2003-01 – 2007-12
Supported an in-house hardware simulation accelerator and performed compiler verification using the GNU toolchain.
National Semiconductor
Principal Software Engineer
1999-01 – 2003-12
Specified extensions to the in-house SoC design tool Virtual Silicon for mixed-signal simulation and conducted verification for large ASICs using Verilog, C++, Debussy, and Mentor's Seamless tools. Represented National Semiconductor on the Accellera Verilog-AMS and SystemVerilog standards committees.
Cameron EDA
Founder/Consultant
1997-01 – Present
Independent consulting practice concentrating on software development, analog and mixed-signal methodology, and heterogeneous parallel computing. Built ParC, an extended C++ meta-compiler, and a just-in-time optimizing model compiler for Spice3.
MetaSoftware/Avanti
Senior Software Engineer
1995-01 – 1997-12
Developed a Verilog-A/MS simulator integrated with HSpice and a digital simulator, producing the world's first compiled-code Verilog-A simulator demonstrated at DAC 1996. Built a dynamic model loader for HSpice and performed porting work across multiple operating systems.
Chronologic/ViewLogic
Developer
1993 – Present
Held sole responsibility for the development and productization of fast Verilog simulation.